the powerpc 750 and powerpc 740 microprocessors are low-power 32-bit implementations of the powerpc reduced instruction set computer (risc) architecture. the powerpc 750 and the powerpc 740 microprocessors differ only in that the powerpc 750 features a dedicated l2 cache interface with on-chip l2 tags. both are software-compatible and bus-compatible with the powerpc 603e and mpc7400 micro- processors, and the powerpc 740 is pin-compatible as well. powerpc 750/740 microprocessors are fully jtag-compliant. superscalar microprocessor the powerpc 750/740 microprocessors are superscalar, capable of issuing three instructions per clock cycle into six independent execution units: two integer units load/store unit floating-point unit system register unit branch processing unit the ability to execute multiple instructions in parallel, to pipeline instructions, and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for powerpc 750/740 systems. power management the powerpc 750/740 microprocessors feature a low- power 2.6-volt or 1.9-volt design with three power- saving modes?oze, nap and sleep. these user-programmable modes progressively reduce the power drawn by the processor. these low-power microprocessors offer dynamic power management to selectively activate functional units as they are needed by the executing instructions. both microprocessors also provide a thermal assist unit and instruction cache throttling for software- controllable thermal management. cache and mmu support the powerpc 750/740 microprocessors have separate 32-kbyte, physically-addressed instruction and data caches. both caches are eight-way set-associative. the additional dedicated l2 cache interface with on- chip l2 tags (shown at right) is provided only by the mpc750fact/d rev. 6 fact sheet m otorola p ower pc 750 and p ower pc 740 m icroprocessors motorola powerpc 750 microprocessor 32b address 17b address 64b data 64b data system register unit bus interface unit l2 control / tags system bus l2 cache integer unit integer unit floating point unit mmu inst. cache mpc750 only mmu data cache load/store unit instruction unit branch processing unit powerpc 750/740 microprocessor block diagram
powerpc 1xx, 6xx and 7xx part number key 100, 600, or 700 series device number (106, 107, 603, 740, 745, 750, 755) mpc 750 a rx 200 l h product code ppc sample xpc xc qualified mpc qualified part/module modifier a alpha (original) b dgo process e 603 enhanced performance p enhanced & lower voltage r 603e in hip3 process c 2:1 (106 only) d 5:2 (106 only) l full spec all modes frequency 2-3 digits application modifier bus ratio r105 t ext. temp. (-40 to 105 ) -or- application relief revision package fe cqfp rx cbga w/o lid px pbga w/o lid powerpc 750 microprocessor. powerpc 750/740 microprocessors contain separate memory management units (mmus) for instructions and data, supporting 4 petabytes (2 52 ) of virtual memory and 4 gigabytes (2 32 ) of physical memory. access privileges and memory protection are controlled on block or page granularities. large, 128-entry translation lookaside buffers (tlbs) provide efficient physical address translation and support for demand virtual- memory management on both page- and variable-sized blocks. flexible bus interface powerpc 750/740 microprocessors have a 64-bit data bus and a 32-bit address bus. support is included for burst, split and pipelined transactions. the interface provides snooping for data cache coherency. both microprocessors maintain mei coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as dma devices. cpu speeds ?internal 200, 233 and 266 mhz cpu bus dividers powerpc 740 200-266 mhz 300 and 333 mhz x3, x3.5, x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8 x3, x3.5, x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8 powerpc 740 300-333 mhz 300, 333, 366 and 400 mhz bus interface 64 bits 64 bits 64 bits instructions per clock 3 (2 + branch) 3 (2 + branch) 3 (2 + branch) l2 cache 256, 512 kbyte 1 mby te typical/maximum power dissipation 5.7w/7.9w @ 266 mhz 4.2w/6.0w @ 333 mhz 5.8w/8.0w @ 400 mhz die size 67 mm 2 67 mm 2 67 mm 2 package 255 cbga 255 cbga 255 cbga process 0.29 5lm cmos 0.25 5lm cmos 0.25 5lm cmos vo l t a g e 3.3v i/o, 2.6v internal 3.3v i/o, 1.9v internal 3.3v i/o, 1.9v internal specint95 (estimated) 11.5 @ 266 mhz 14.4 @ 333 mhz 18.8 @ 400 mhz specfp95 (estimated) 6.9 @ 266 mhz 8.7 @ 333 mhz 12.2 @ 400 mhz other performance 488 mips @ 266 mhz 610 mips @ 333 mhz 733 mips @ 400 mhz execution units integer, floating-point, branch, load/store, system register integer, floating-point, branch, load/store, system register integer, floating-point, branch, load/store, system register x3, x3.5, x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8 powerpc 750 300-400 mhz 200, 233 and 266 mhz 64 bits 3 (2 + branch) 256, 512 kbyte 1 mby te l1 cache 32-kbyte instruction 32-kbyte data 32-kbyte instruction 32-kbyte data 32-kbyte instruction 32-kbyte data 32-kbyte instruction 32-kbyte data 5.7w/7.9w @ 266 mhz 67 mm 2 core-to-l2 frequency 1:1, 1.5:1, 2:1, 2.5:1, 3:1 1:1, 1.5:1, 2:1, 2.5:1, 3:1 255 cbga 0.29 5lm cmos 3.3v i/o, 2.6v internal 12.0 @ 266 mhz 7.4 @ 266 mhz 488 mips @ 266 mhz integer, floating-point, branch, load/store, system register x3, x3.5, x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8 powerpc 750 200-266 mhz 1atx35906-6 printed in usa 5/00 hibbert litrisc contact information motorola offers user? manuals, application notes and sample code for all of its processors. in addition, local support for these products is also provided. this information can be found at: http://motorola.com/powerpc/ for all other inquiries about motorola products, please contact the motorola customer response center at: phone: 800-521-6274 or http://motorola.com/semiconductors powerpc 750/740 cpu summary ?2000 motorola, inc. all rights reserved. printed in the u.s.a. motorola and the are registered trademarks of motorola, in c. powerpc, the powerpc logo, powerpc 603e, powerpc 740 and powerpc 750 are trademarks of international business machines corporation and used under license therefrom. this document contains information on a new product under devel opment. specifications and information herein are subject to change without notice.
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